TSMC’s advanced-packaging line is the single tightest physical constraint on AI compute. Here is who controls it, by the numbers.
What is the tightest constraint on AI GPU supply in 2026?
The tightest physical constraint on AI GPU supply in 2026 is not silicon, fabs, or even HBM memory; it is TSMC’s CoWoS advanced-packaging capacity, the line that bonds GPU logic and high-bandwidth memory onto a single interposer. Every Nvidia data-center GPU of the Blackwell and Rubin generations has to pass through that step, and there is currently only one supplier in the world running it at the volume and yield the AI buildout demands. Understanding CoWoS capacity 2026 — who holds it and who is booked out — explains GPU availability better than any chip spec sheet.
The acronym hides what it does. CoWoS stands for Chip-on-Wafer-on-Substrate: the GPU die and a stack of HBM chips are mounted side by side on a silicon interposer, then the whole assembly is placed on a substrate. Without that interposer, an H200 or a Rubin GPU is just a pile of unconnected dies. You cannot ship the chip until it is packaged, and packaging is exactly where the line forms.
This is why CoWoS capacity 2026 has become the number that quietly governs the entire AI capital cycle. You can announce a new fab, a new model, or a $100 billion data-center commitment, but if the packaging line is booked, none of it converts into deliverable accelerators on the original timeline. The bottleneck moved downstream, and most of the market is still watching the wrong stage.
How fast is CoWoS capacity 2026 actually scaling?
TSMC is scaling CoWoS capacity from roughly 35,000 wafers per month in late 2024 to a record 75,000 in 2025 and a projected 120,000 to 130,000 wafers per month by the end of 2026, an effective quadrupling in two years. TrendForce frames the advanced-packaging line as growing at a compound annual growth rate of more than 80% from 2022 to 2027, faster than almost any other node in the company’s history. That is why CoWoS capacity 2026 is the number supply-chain analysts watch most closely.
And yet it is still not enough. That is the paradox at the center of this story: capacity is exploding and the bottleneck refuses to clear. TrendForce projects total CoWoS wafer demand climbing from 370,000 wafers in 2024 to 670,000 in 2025 and roughly 1 million in 2026, while AI accelerator wafer demand is forecast to rise eleven-fold between 2022 and 2026. Supply is sprinting; demand is on a rocket.
Jensen Huang put it plainly: Nvidia quadrupled its advanced-packaging capacity in under two years and packaging is still the bottleneck. He has since reframed manufacturing constraints as a ‘two-to-three year problem’ rather than something that resolves in a single product cycle. TSMC CEO C.C. Wei has said CoWoS capacity remains sold out through 2025 and into 2026. When both the buyer and the supplier agree the line is full, the shortage is structural, not a hiccup.
The chart below stacks the two facts that matter most: how fast the line is growing, and how little of it is actually available to anyone other than the anchor tenant.
A GPU die can be fabbed, and HBM stacks can be made, but neither ships as a usable accelerator until CoWoS bonds them onto an interposer. Packaging is the last gate, so it becomes the binding constraint the moment demand outruns it.
How much CoWoS capacity has Nvidia locked for 2026?
60%+
of 2026 CoWoS capacity
Reserved by Nvidia as anchor tenant
~595k
Nvidia 2026 CoWoS wafers
Of ~1M total global demand
85%+
Locked by top customers
Under 15% left for everyone else
11x
AI wafer demand growth
2022 to 2026, per TrendForce
Nvidia has reportedly secured more than 60% of TSMC’s total CoWoS capacity for both 2025 and 2026, making it TSMC’s packaging anchor tenant by a wide margin. In raw volume, industry estimates put Nvidia’s 2026 CoWoS wafer demand at around 595,000 wafers, about 60% of the roughly one million wafers of total global demand, with the bulk routed to its Rubin architecture.
The rest of the line is divided among a tight club. Broadcom is estimated at roughly 150,000 wafers (about 15%), carrying custom silicon for Google’s TPUs, Meta, and OpenAI. AMD sits near 105,000 wafers (about 11%) for its MI355 and MI400 accelerators. Amazon, Marvell, MediaTek, and a handful of others split most of what remains. The critical line from analysts: major customers have locked in more than 85% of TSMC’s total CoWoS production, leaving under 15% for second-tier players and startups.
That allocation is the part of the AI supply chain almost no buyer ever sees. When a startup rents H200s from a neocloud, or a lab waits months for a Rubin reservation, the gating factor traces back to a packaging-allocation contract signed years earlier between Nvidia and TSMC. The 60% lock is the most important number in AI capital that does not appear on a single product spec sheet.
“The 60% lock is the most important number in AI capital that never appears on a product spec sheet.”
On Nvidia’s CoWoS anchor position
| Customer | Est. 2026 CoWoS wafers | Approx. share | Primary products |
|---|---|---|---|
| Nvidia | ~595,000 | ~60% | Rubin, Blackwell GPUs |
| Broadcom | ~150,000 | ~15% | Google TPU, Meta, OpenAI ASICs |
| AMD | ~105,000 | ~11% | MI355, MI400 accelerators |
| Marvell | ~55,000 | ~5% | AWS, Microsoft custom silicon |
| Amazon (Alchip) | ~50,000 | ~5% | Trainium-class accelerators |
| MediaTek | ~20,000 | ~2% | Google TPU v7e/v8e |
| Total demand | ~1,000,000 | 100% | All AI accelerators |
Why does CoWoS stay a bottleneck even as capacity quadruples?
CoWoS stays a bottleneck because demand is compounding faster than even an 80%-CAGR supply ramp can absorb, and because each new GPU generation consumes more packaging per chip than the one before it. The Rubin generation is the clearest example: Nvidia’s Vera Rubin NVL72 system pairs 36 Vera CPUs with 72 Rubin GPUs, a six-chip design that Huang has called potentially the largest product launch in Taiwan’s history, requiring nearly two million parts per system.
Bigger, more capable accelerators are not packaging-neutral. As GPUs adopt larger interposers and stack more HBM, each chip eats a larger slice of CoWoS area. TSMC’s roadmap underscores the trajectory: today’s largest interposer is a 5.5-reticle-size version at 98% yield, scaling to a 14-reticle version integrating 20 HBM stacks by 2028 and up to 24 stacks by 2029. The unit of demand keeps inflating, so wafer-count growth understates the real strain.
There is also a yield-and-time reality. CoWoS-L, the variant Nvidia leans on most heavily for its top accelerators, is reportedly fully booked, and the most advanced packaging steps cannot be spun up overnight. New cleanroom space, bonders, and trained capacity take quarters to come online. That lag is precisely why Huang reframed the constraint as a multi-year problem rather than a single-cycle squeeze.
The blunt version: you can double a packaging line in 18 months, but if your customers are simultaneously tripling their per-chip packaging footprint and the overall market is growing 11x in wafers, the line stays sold out the entire time.
Capacity quadrupling and the bottleneck persisting are not a contradiction. When per-GPU packaging area rises with every generation and total AI wafer demand grows 11x from 2022 to 2026, an 80%-CAGR sWhat does CoWoS cost, and why is it now a profit driver?
A single CoWoS wafer now sells for around $10,000, an average selling price approaching TSMC’s 7nm logic node, which is turning advanced packaging from a low-margin afterthought into a strategic profit driver. For most of its history, packaging was the unglamorous back end of the supply chain. AI demand inverted that economics in under two years.
The math is striking. At roughly $10,000 per wafer and a projected 120,000-to-130,000 wafers per month by late 2026, the CoWoS line alone represents an annualized revenue run-rate well into the tens of billions of dollars. TrendForce notes that while advanced-packaging margins still sit below TSMC’s corporate average, they are expected to become a key profit driver as economies of scale expand, helped by a relatively lighter capital-expenditure structure than leading-edge logic.
For Nvidia and its rivals, that ASP flows straight into the cost basis of every accelerator. CoWoS is no longer a rounding error on a GPU bill of materials; it is a meaningful and rising line item. And because the supplier holds pricing power on a sold-out line, the cost of packaging is one of the few inputs in the AI stack that is structurally resistant to the usual deflation. That has direct consequences for anyone modeling future inference costs.
Inference-cost optimism usually assumes silicon gets cheaper every year. But a sold-out packaging line priced near 7nm logic is a cost input that resists deflation. If you are forecasting 2027 token prices, CoWoS pricing power is the variable most likely to disappoint.
Can Amkor, ASE, or Intel break the CoWoS monopoly?
The most credible relief valves for CoWoS are TSMC outsourcing simpler steps to Amkor, ASE, and SPIL, plus Intel’s EMIB and Foveros packaging being eyed as a genuine second source, but none of these fully replaces high-end CoWoS-L before 2027 at the earliest. The single-supplier risk is real, and the entire industry knows it.
TSMC is already shedding load. Estimates suggest it will hand 240,000 to 270,000 wafers a year to OSAT partners in 2026, mostly Amkor (around 180,000 to 190,000) and SPIL (around 60,000 to 80,000), to free its own lines for the most demanding work. ASE projects its advanced-packaging sales to double in 2026. Nvidia has also snapped up additional U.S. packaging capacity as TSMC expands in Arizona, where output is expected to grow 1.8-fold year over year in 2026.
The most interesting wildcard is Intel. Its EMIB embedded-bridge approach and Foveros 3D stacking are not raw-performance equals to CoWoS-L, but they are mature enough for AI inference ASICs and modular SoCs, and Intel’s CFO has signaled foundry packaging deals ‘in the billions per year.’ Chipmakers fabbing logic at TSMC Arizona are now reportedly eyeing Intel’s New Mexico facility for domestic packaging, a notable shift in a market TSMC has owned. Longer term, panel-level packaging and glass substrates open more options, but commercial deployments are not expected until 2027 to 2028.
So the monopoly bends before it breaks. Outsourcing and second sources will absorb the easier work and trim the worst of the shortage, but the highest-end interposers that Rubin-class GPUs require remain a TSMC near-monopoly through this cycle.
Pros
Cons
What should AI builders and investors actually do about it?
CoWoS is the load-bearing wall of the AI economy
The practical takeaway is to treat CoWoS allocation as a leading indicator: track packaging bookings, not just GPU announcements, because the packaging line tells you 12 months ahead whether GPU supply and pricing will loosen. Model launches and fab groundbreakings are lagging signals; the packaging contract is the one that already decided the next year of availability.
For builders renting compute, the lesson is counterparty mapping. Your real exposure is not the cloud you sign with; it is the packaging allocation upstream that determines whether your provider can actually field the GPUs it promised. When CoWoS-L is reported sold out through 2026, that is your cue to lock reservations early and assume spot pricing stays elevated, regardless of how many new chips get announced on stage.
For investors, CoWoS is the cleanest single proxy for the health and the chokepoints of the entire AI buildout. The 60% Nvidia lock measures durable demand and pricing power; the OSAT outsourcing and Intel second-sourcing measure how quickly the constraint diversifies. Watch both numbers. The day under-15% of the line is no longer reserved for second-tier buyers is the day the AI compute shortage genuinely starts to ease, and not before.
Builder’s take
I build AI orchestration software at Cyntr and run an agent-feed product at Loomfeed, so I sit downstream of every GPU shortage. From where I stand, CoWoS is the most underpriced variable in the whole AI economy.
- Everyone benchmarks the model. Almost nobody models the substrate. The cost curve that actually decides whether your inference bill falls in 2027 is set on a packaging line in Taiwan, not in a research lab.
- The 60% Nvidia lock is not a scandal, it is a contract. If you are building on rented GPUs, your real counterparty risk is a packaging allocation you will never see on any invoice.
- I treat CoWoS as a leading indicator. When CoWoS-L is ‘sold out through 2026,’ that is your 12-month warning that spot GPU pricing and cloud reservations are about to stay ugly, no matter how many fabs get announced.
- The second-source story (Amkor, ASE, Intel EMIB) is the only thing that breaks the single-point-of-failure. As a builder I want it to work even more than Nvidia does, because diversified packaging is what eventually makes compute a commodity instead of a privilege.
Frequently asked questions
CoWoS stands for Chip-on-Wafer-on-Substrate, TSMC’s advanced-packaging technology that bonds a GPU die and high-bandwidth memory stacks onto a single silicon interposer. Every Nvidia data-center GPU must pass through this step, so it is the final gate before a chip can ship. In 2026 it is the tightest physical constraint on AI GPU supply, ahead of silicon or HBM memory.
Nvidia has reportedly locked more than 60% of TSMC’s total CoWoS capacity for both 2025 and 2026, making it TSMC’s packaging anchor tenant. Industry estimates put its 2026 demand near 595,000 wafers out of roughly one million total, mostly for its Rubin GPU architecture.
TSMC is scaling CoWoS from about 35,000 wafers per month in late 2024 to a record 75,000 in 2025, and a projected 120,000 to 130,000 wafers per month by the end of 2026. That is roughly a quadrupling in two years, an 80%-plus compound annual growth rate, yet the line remains booked.
Demand is growing faster than supply. TrendForce projects AI accelerator wafer demand rising 11x between 2022 and 2026, and each new GPU generation uses larger interposers and more HBM stacks, so per-chip packaging area keeps rising. The result is that even an 80%-CAGR ramp arrives short, and CoWoS-L stays sold out.
TSMC outsources simpler steps to Amkor, ASE, and SPIL, with an estimated 240,000 to 270,000 wafers a year handed off in 2026. Intel’s EMIB and Foveros are being eyed as a genuine second source for inference ASICs, though not a raw-performance equal for top GPUs. High-end CoWoS-L remains a TSMC near-monopoly through this cycle.
Industry estimates put the average selling price of a single CoWoS wafer near $10,000, approaching TSMC’s 7nm logic node. That has turned advanced packaging from a low-margin step into a strategic profit driver, and it adds a rising, deflation-resistant cost to every AI accelerator.
Primary sources
- Nvidia Secures 60% of CoWoS Capacity — Astute Group
- TSMC sees AI wafer demand rising 11x, CoWoS 80% CAGR — TrendForce
- TSMC set to expand CoWoS to record 75,000 wafers in 2025 — TrendForce
- Nvidia snaps up AI chip packaging capacity as TSMC expands in U.S. — CNBC
- Who Will Divide Up the CoWoS Production Capacity in 2026? — 36Kr
- Intel’s EMIB and Foveros eyed as CoWoS capacity stays stretched — Tom’s Hardware
- TSMC CoWoS wafer ASP nears 7nm; packaging a key profit driver — TrendForce
- Jensen Huang flies to TSMC as Vera Rubin ramp strains supply chain — TechTimes
Last updated: June 1, 2026. Related: Capital.
